Senior Digital RTL Design Engineer

Job Title: Senior Digital RTL Design Engineer

Location: Germany & Austria

Job Type: Permanent

Salary: DOE

Role Overview:

You will be delivering high quality and best performing results for different network solutions and protocols from specification to the implemented netlist.

There are opportunities to be involved in multiple levels of RTL design, from chip level integration of IPs, purely digital IP blocks, and down to close interaction with analog mixed-signal IP.

Key Responsibilities:

-Analyse and understand complex design specifications or industry standards, and translate them into microarchitecture specifications, including formulating requirements. -Develop and maintain complex digital IPs at the RTL level based on microarchitecture specifications. Including ownership of IP blocks or sub-blocks. -Support those digital IP blocks from their inception through design and verification to tape out and bring up. -Understand and debug identified errors together with the functional verification team. -Create or support creation of internal as well as customer-facing product specification documentation. -Closely work together with other teams, such as the architecture, verification, backend, and firmware teams. -Participate in cross-functional groups to support a successful and on-time product release.

Skills Required:

-B.S./M.S. degree on Electrical Engineering, Physics, Computer Engineering, Information Technology or related subject with emphasis on hardware design. -A minimum of 7 years work experience, including internships. -Experience in HDL design, preferrably using SystemVerilog. -Experience in working with Cadence XCELIUM, or a comparable simulator. -Basic knowledge of timing constraints and synthesis is a plus. -Knowledge of functional verification (UVM) and SystemVerilog assertions is a plus. -Knowledge about communication principles (such as line codes, retry protocols, CRC, FEC) and experience with different protocols (like UCIe, PCIe, Ethernet, AMBA AXI, or CHI) is a plus. --span

B.S./M.S. degree on Electrical Engineering, Physics, Computer Engineering, Information Technology or related subject with emphasis on hardware design. -A minimum of 7 years work experience, including internships. -Experience in HDL design, preferrably using SystemVerilog. -Experience in working with Cadence XCELIUM, or a comparable simulator. -Basic knowledge of timing constraints and synthesis is a plus. -Knowledge of functional verification (UVM) and SystemVerilog assertions is a plus. -Knowledge about communication principles (such as line codes, retry protocols, CRC, FEC) and experience with different protocols (like UCIe, PCIe, Ethernet, AMBA AXI, or CHI) is a plus. --span