ASIC / NoC Verification & Solutions Senior Engineer- Qualcomm - Guyancourt, France

QITC NoC solution tools include a full suite of automated interconnect design and verification tools that improve user productivity. In particular, NoC verification tools include state-of-the-art Verification IPs, UVM benches, and scoreboards, used to check NoC assembly and NoC-level features. The UVM bench is automatically generated by the software, allowing it to map to all NoC varying topologies and features.

You will join the Solutions deployment team with the mission of deploying and supporting the QITC NoC Verification technology across all the SoCs in Qualcomm's portfolio (Mobile, Automotive, Servers, IoT, Connectivity, etc.). The job involves providing verification support, including analyzing complex scenarios of NoC simulations, understanding the behavior of verification components, benches, and their associated automation tools in compliance with current ASIC verification standards like UVM.

This is a challenging position with a lot of inter-team communication. You will be working on the most innovative technologies, surrounded by experts and users of our technology from various teams (SoC Architecture, HW and SW Design, Verification, Debug, Post Silicon) worldwide.

Responsibilities:

In your role, you will:

• Collaborate regularly with highly skilled experts across different teams (Architecture, Hardware, Software, Verification, Emulation, etc.) to ensure our Verification technology is used efficiently in Qualcomm SoCs.

• Contribute to the definition and enhancement of the NoC Verification environment and its configuration in the various SoCs.

• Be responsible for the technical support of new NoC verification solutions.

• Help resolve NoC testbench or DUT simulation issues.

• Participate in defining new Verification solutions and improvements for our technology.

• Develop in-depth technical material and organize training sessions for different teams worldwide.

The working environment will consist of: Verilog, SystemVerilog, UVM, Python, Linux, Shell, Git, Synopsys, or Mentor Graphics verification tools.

Do you have experience in Verilog?, Do you have a Master's degree?, * Experience in using or designing UVM components, benches, or VIPs.

• Strong analytical skills for debugging in simulation, emulation, or silicon bring-up environments.

• Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI/NoC concepts.

• Understanding of overall SoC development flow: SoC architecture, RTL design and verification, SoC performance and DDR memory channel, physical implementation, silicon debug.

• Good knowledge of system-level features such as memory-mapping, MMUs, Quality of Service, cache infrastructure, security schemes, etc.

• Proficiency in Python & Perl scripting.

• Ability to quickly react and adapt to changes.

• Excellent communication skills.

Minimum Qualifications:

• Master's degree in Microelectronics, Computer Science, or a related field.

• Standard SoC knowledge: Multimedia IPs, GPU, multi-core CPU architecture, Processors, Caches, memory controllers, interconnects, and related design, integration, and verification challenges.

Preferred Qualifications:

• 2-5 years of solid experience in verification and/or design for SoC/ASIC engineering development cycles.

• Experience in using or designing UVM components, benches, or VIPs., * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

• Friendly and collaborative working environment.

• Salary, stock, and performance-related bonus.

• Maternity/Paternity Leave.

• Employee stock purchase scheme.

• Matching pension scheme.

• Education Assistance.

• Life, Medical, Income, and Travel Insurance.

Keywords:

• SoC, ASIC, Verification, Simulation debug, Interconnect, Cache, CPU, GPU, Coherency, Debug

Qualcomm France S.A.R.L., Qualcomm France-QITC's mission is to develop and deploy highly configurable custom-built interconnect hardware IPs (NoCs), software tools, and exploration and verification methodologies. This enables SoC integration teams to quickly assemble and verify SoCs with the desired Power Performance Area (PPA) characteristics. QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions. Qualcomm Interconnect Technology Center (QITC) has been breaking ground in interconnect design for 15 years and continues to innovate and deliver technology in line with the latest evolutions in SoC design.